This invention generally relates to integrated circuit physical design and power supply integrity, and more specifically relates to a method of reducing power rail transients on integrated circuits.
Approaches which are currently being used to try to reduce power rail transients on integrated circuits include adding more power and ground bonds, and adding on chip capacitance. In effect, these approaches attempt to cure a symptom rather than address the root cause of the problem. Additionally, as voltage levels on newer CMOS (complementary metal oxide semiconductor) technologies continue to decrease, the costs of adding enough of either power and ground bonds or on chip capacitors will increase substantially. As the area needed on die de-coupling capacitors becomes a limiting factor on die size, die cost will increase, and adding additional power bonds and/or adding package power planes will increase package cost.
In a typical integrated circuit, each latch/flip flop is controlled by the edge of a clock feeding a combinational logic path to the next clocked storage device. For power transient analysis, the transient load on each of the flip flops/latches is modelled as a switch controlled by the clock, and the design is synchronous, meaning each switch closes simultaneously. The idea of an ideal synchronous clock has been the basis of most all logic design tools used presently in the industry. While this ideal does simplify the logic design, it also maximizes the differential voltage drop between the VDD/VSS nets due to power supply inductance and resistance. While an asynchronous design would not have as much of a problem, asynchronous design tools and techniques are immature and are not currently widely used in integrated circuit design.
A low cost solution which reduces the need for any of these solutions and which actually addresses the root cause of the problem is needed in the industry.
A general object of an embodiment of the present invention is to provide a method of reducing power rail transients on integrated circuits.
Another object of an embodiment of the present invention is to provide a method of reducing power rail transients on integrated circuits without having to add more power and ground bonds, and reducing the need for added on chip capacitance.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a method of reducing power rail transients on integrated circuits by controlling clock skew in a manner which minimizes dI/dT current demands of the integrated circuit. The method provides that the phase of the clock to latches/flip flops is shifted in order to spread out the number of simultaneous switching elements. By controlling the number of simultaneous switching devices, a significant reduction in time rate of current demanded from the power rails can be achieved, thereby reducing the magnitude of VSS/VDD voltage transients due to parasitic inductances and resistances supplying power to the integrated circuit. Theoretically, the entire timing spread of the slack graph for clock skew can be used to control the number of simultaneous switching devices. Ideally, the clock inputs to the storage elements are skewed such that dIC/dT is minimized while still meeting pre-determined bounding conditions. Preferably, the number of clock buffers and their associated wire is also minimized for all conditions.